gtps4m0v | System Generation |
The following describes the preliminary storage requirement formulas for the MPIF product. The formulas have not been put through any formal validation process; therefore, they are subject to change as experience is gained.
TABLE NAMES:
For the formulas that follow:
Formula: (X × IL) + HL = RS
Item | IL | X | HL | RS |
---|---|---|---|---|
DCTCDB | 120 | V9 | 16 | C |
DCTCWA | 160 | V10 | 8 | C |
| 32 | V6 | 0 | C |
DCTDNT | 80 | V8 | 16 | C |
DCTICD | 24 | V12 | 8 | C |
DCTIGT | 56 | V11 | 56 | C |
DCTGFN | 40 | V4 | 16 | C |
DCTMGT | 0 | 0 | 0 | 376 |
DCTPAN | 72 | V8 | 16 | C |
DCTPDT | 216 | V5 | 16 | C |
DCTRFN | 120 | V3 | 16 | C |
DCTSCT | 66 | V2 | 16 | C |
DCTTRC | 0 | 0 | 0 | 4096 |
The term multi-system request block (MSRB) describes MPIF's use of system work blocks (SWB) to hold input and output data. SWB is a generally used core block type. MSRB refers to MPIF data in an SWB that fits the DCTMRB format. The following formulas calculate the storage requirements for MPIF's use of SWBs.
The number of SWBs required by MPIF is calculated as follows:
I_O = number of SWBs required for the I/O activity. N = number of SWBs required for the I/O activity and the miscellaneous MPIF requirements. RS = the number of bytes of storage required for SWBs. (For computation of IO, use the larger of the following two values.) I_O = ((queue depth) + 5) × V5 or I_O = .10 × ( # of 381-byte blocks + # of 1055-byte blocks + number of 4096-byte blocks) + 20 (1.5 × V6) + I_O = N
The amount of storage required by the MPIF feature for SWBs is calculated as follows:
1024 = RS
The following factors are important in calculating the storage size required for staging buffers:
THE CONFIGURATION: Three loosely coupled complexes interconnected together 1 has 6 processors (sample system is in this complex) 2 has 6 processors 3 has 2 processors SWBs: 111 616 Assuming: I_O = 200 N = 218 STAGING BUFFERS: 552 960 Assume user-specified size for all paths is 4096. 1024 + 4096 = 5120 3 × V5 × 5120 = 3 × 36 × 5120 = 552 960 TABLES: 46 168 V1 = 10 systems V2 = 11 systems V3 = 2 number of users in this system V4 = 24 number of users in the complex V5 = 36 number of paths attached to this processor 2 each to 5 LC systems for IPC 2 each to 13 systems for any-to-any connectivity V6 = 4 3088s V7 = 32 devices per 3088 V8 = 26 V9 = 59 number of connections V10 = 128 DCTCDB = 7096 DCTCWA = 20616 DCTDNT = 2090 DCTGFN = 976 DCTMGT = 376 DCTPAN = 1888 DCTPDT = 7792 DCTRFN = 496 DCTSCT = 742 DCTTRC = 4096 *********************************************************************** * TOTAL CORE REQUIREMENTS FOR SAMPLE CASE 710 744 ***********************************************************************