gtps4m0vSystem Generation

Storage Requirements for Multi-Processor Interconnect Facility

The following describes the preliminary storage requirement formulas for the MPIF product. The formulas have not been put through any formal validation process; therefore, they are subject to change as experience is gained.

Storage Required For Tables

TABLE NAMES:

DCTCDB
Connection Definition Block (CDB)

DCTCWA
MPIF CCW Area Table (CWA)

DCTDNT
Directory Update Notification Table (DNT)

DCTGFN
Global Function Name Directory (GFND)

DCTMGT
MPIF Global Table (MGT)

DCTPAN
Path Activation Notification Table (PAN)

DCTPDT
Path Definition Table (PDT)

DCTRFN
Resident Function Name Directory (RFND)

DCTSCT
System-to-System Connection Table (SSCT)

DCTTRC
MPIF Trace Block (MTRC)

For the formulas that follow:

 C = 
compute the storage requirement as per algorithm.

 HL = 
header length.

 IL = 
item length.

 RS = 
required storage which can be given or have to be computed using the formula.

 V1 = 
number of systems connected to this system.

 V2 = 
number of systems connected to this system plus one (1).

 V3 = 
number of MPIF users which might be active in this system.

 V4 = 
number of MPIF users which might be active in the attached processors.

 V5 = 
number of paths which might be attached to this system.

 V6 = 
number of CTC communication links that might be attached to this system.

 V7 = 
number of addresses per CTC communication link.

 V8 = 
V1 × V3

 V9 = 
number of connections which will be made in this system. This has to include 1 CDB per path for the MPIF to MPIF connection plus the number of connections anticipated for each user in this system.

 V10 = 
V6 × V7

 X = 
variables, refer to description for the given label.

 V11 = 
number of processors in a loosely coupled complex.

 V12 = 
V11 times the maximum number of paths between processors in a loosely coupled complex.

Formula: (X × IL) + HL = RS

Item IL X HL RS
DCTCDB 120 V9 16 C
DCTCWA 160 V10 8 C

32 V6 0 C
DCTDNT 80 V8 16 C
DCTICD 24 V12 8 C
DCTIGT 56 V11 56 C
DCTGFN 40 V4 16 C
DCTMGT 0 0 0 376
DCTPAN 72 V8 16 C
DCTPDT 216 V5 16 C
DCTRFN 120 V3 16 C
DCTSCT 66 V2 16 C
DCTTRC 0 0 0 4096

Storage Required For Control Blocks

DCTMRB (Multi-System Request Block)

The term multi-system request block (MSRB) describes MPIF's use of system work blocks (SWB) to hold input and output data. SWB is a generally used core block type. MSRB refers to MPIF data in an SWB that fits the DCTMRB format. The following formulas calculate the storage requirements for MPIF's use of SWBs.

The number of SWBs required by MPIF is calculated as follows:

    I_O = number of SWBs required for the I/O activity.
      N = number of SWBs required for the I/O activity and the
          miscellaneous MPIF requirements.
     RS = the number of bytes of storage required for SWBs.
 
   (For computation of IO, use the larger of the following two values.)
 
          I_O =  ((queue depth) + 5) × V5
   or
          I_O =  .10 × ( # of 381-byte blocks + # of 1055-byte blocks
                + number of 4096-byte blocks) + 20
 
          (1.5 × V6) + I_O = N

The amount of storage required by the MPIF feature for SWBs is calculated as follows:

          1024 = RS

Storage Required for Staging Buffers

The following factors are important in calculating the storage size required for staging buffers:

  1. Each MPIF path is made up of 2 physical links: one is used for reading and the other for writing.
  2. The size of the staging buffers can vary by link. The staging area size is forced to a doubleword boundary.
  3. A control area size is added to the user-specified size for the staging buffer of a path. This control area size is equal to 1024 bytes, which is the size of an SWB.
  4. Two staging buffers are required for read links while 1 staging buffer is required for write links.

Sample Case for Storage Requirements

THE CONFIGURATION:
 
Three loosely coupled complexes interconnected together
 
    1 has 6 processors  (sample system is in this complex)
    2 has 6 processors
    3 has 2 processors
 
SWBs:                                                        111 616
    Assuming:
       I_O = 200
         N = 218
 
STAGING BUFFERS:                                             552 960
       Assume user-specified size for all paths is 4096.
       1024 + 4096 = 5120
       3 × V5 × 5120 =  3 × 36 × 5120 = 552 960
 
TABLES:                                                       46 168
       V1 = 10 systems
       V2 = 11 systems
       V3 = 2  number of users in this system
       V4 = 24 number of users in the complex
       V5 = 36 number of paths attached to this processor
               2 each to 5 LC systems for IPC
               2 each to 13 systems for any-to-any connectivity
       V6 = 4  3088s
       V7 = 32 devices per 3088
       V8 = 26
       V9 = 59 number of connections
      V10 = 128
 
  DCTCDB =   7096
  DCTCWA =  20616
  DCTDNT =   2090
  DCTGFN =    976
  DCTMGT =    376
  DCTPAN =   1888
  DCTPDT =   7792
  DCTRFN =    496
  DCTSCT =    742
  DCTTRC =   4096
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* TOTAL CORE REQUIREMENTS FOR SAMPLE CASE                    710 744
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