gtps1m29 | System Macros |
Use this system macro to create an entry control block (ECB) and permit the control program (CP) to transfer control to another program that is then free to use any CP macros.
Format
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When CBRW=Ry is specified, Rx designates a general purpose register which must point to an 8-byte field formatted as a CBRW. The block address in the CBRW must be a system virtual memory (SVM) address that will be valid on the target I-stream.
When CXFRC macro processing is complete, the 8-byte field pointed to by Ry will be formatted as an empty CBRW.
The CXFRC post interrupt will attach the storage at the SVM address to the address space of the created ECB (the ECB virtual memory), and initialize CBRW 0 with the data passed. The SVM address in the CBRW will be converted to the appropriate ECB virtual address.
There is no default. RTTMSG has no meaning when ECB=DEFER is used.
Entry Requirements
The EXEC parameter must specify a general purpose register that contains the address of 8 bytes of code (normally an enter expansion) that will be processed when the ECB is selected for processing.
Return Conditions
Examples
Requests a DSECT describing the parameter list for the CXFRC call. No code is generated.
CXFRC DSECT=YES
An example from the 37x5 interrupt handler shows passing control to a routine for a specific interrupt. The address for the routine to be transferred to (CS05_CCIM) is specified in R6, the default register. ECB creation is deferred, so when the transfer returns, R6 contains the address of the transfer block (SWB) created and IDSXFC is a DSECT mapping this block. The transfer block will be added to the bottom of the Ready list. Registers R0-R2 are specified as being volatile and are saved on the stack.
... LA R6,CS05_CCIM GET ADDR OF 3705 MSG ROUTINE CXFRC EXEC=R6,BLOCK=R6, PRIORITY=LOW,LIST=READY,ECB=DEFER, SAVREG=(R0,R1,R2) IDSXFC REG=R6 Describe Transfer Block ...
An example from a MPIF path error routine illustrates the use of the CBRW. Request an activation of a broadcast program (CBM6_CBB0) specified in R14 with R3 pointing at a core block reference word formatted field (CBM6_CR0). R4 is used to put the block type and size into a storage location (CBM6_CT0) as a part of the field formatted as a core block reference word.
Upon return from the control transfer R14 contains the address of the transfer block created to hold ECB information, since ECB creation is deferred. When the ECB is activated, it is put on the bottom (low priority) of the Ready list. Register R1 is specified as a volatile register and is saved in the stack area. When the transfer returns, the IDSXFC DSECT is used to map the transfer block.
CBM6_CR0 DS F CBRW BLOCK ADDRESS (FOR CXFRC) CBM6_CT0 DS F CBRW TYPE & SIZE (FOR CXFRC) ... ST R4,CBM6_CR0 SET CBRW ADDRESS FOR CXFRC LR R0,R15 SAVE BASE ACROSS MACROS LA R4,L4 4K BLOCK TYPE TYPBC TYPE=R4 GET BLOCK TYPE AND SIZE LR R15,R0 RESTORE BASE REGISTER ST R4,CBM6_CT0 SET TYPE & SIZE FOR CXFRC L R4,CBM6_CR0 RELOAD BASE OF 4K BLOCK LA R14,CBM6_CBB0 LOAD BASE OF BROADCAST * ROUTINE LA R3,CBM6_CR0 SET CBRW POINTER CXFRC EXEC=R14,BLOCK=R14,CBRW=R3, PASS BLOCK TO CBB0 PRIORITY=LOW,LIST=READY,ECB=DEFER, SAVREG=(R1) IDSXFC REG=R14 DESCRIBE TRANSFER BLOCK ...
When this transfer block is taken off the Ready list, it will enter segment COSK. This transfer sets up a call to the program at CPMFRI and creates a deferred ECB. When the transfer is complete, R14 contains the address of the transfer block. If a lowcore condition is detected, control is transferred to the CPMPIND1 routine to either preserve a prior error code or indicate the current error code before returning.
LA R14,CPMFRI load COSK ENTNC address CXFRC EXEC=R14, get transfer block for TZEC BLOCK=R14, function LOWCORE=CPMPIND1, PRIORITY=LOW, LIST=READY, ECB=DEFER, SAVREG=(R0,R1,R2) SPACE 1 LA R15,CT7KEC load TZEC branch vector ... ******** CXFRC unable - set up WAITC error SPACE 1 CPMPIND1 DS 0H CLI CE1SUC(R9),X'00' previous error BNE CPMPIND2 yes - do not clear SUG and SUD SPACE 1 XC CE1SUD(CE1SUG-CE1SUD+1,R9),CE1SUD(R9) clear SUG / SUD SPACE 1 MVI CE1SUC(R9),X'30' set I/O error flag SPACE 1 ******** return from macro ...
This transfer to routine CPMCPSI creates the ECB but since there is no list specified, the address of the ECB is returned in R14 and the address of the post interrupt routine is returned in R2. Observe that the ECB address is put into R9 for use as an ECB.
... LA R14,CPMCPSI Locate 'ENTNC CPSI' CXFRC EXEC=R14, Pass ENTNC addr in R14, BLOCK=R14, Return ECB addr in R9, PIADDR=R2, CXFRC PIA in R2, ECB=IMMED, Make ECB now LIST=NONE, But don't add to list SAVREG=(R0,R1) LR R9,R14 ECB address to R9 ...
The value specified on the PIADDR parameter is used later as input to the $ADPC macro, which adds the acquired ECB to the ready list. See $ADPC-Add Work to a List on Specified I-Stream for more information about the $ADPC macro.