3.1 Starting the Simulator

The simultor controls can be accessed either via the "Simulate" menu, or the button bar. Start a simulation by selecting "Begin Simulation" from the "Simulate" menu, or by pressing the "play" button on the button bar. A scope trace window will appear when you start the simulator, as well as text windows for any "tty" devices in your circuit. If there are any auto execute script files (see Simulation Scripts for details) these will be executed too.

The simulation will be performed with the designated root module at the top-level. The simulator internally expands any module instances in your circuit. Since the path you take to get to a module is significant to the simulator, you cannot jump directly to submodules but must "navigate" your way to them by selecting a module at the current level and by opening it using the menu or the '>' keyboard command. You can leave a module you are in with the '<' keyboard command.

Gate and wire names in sub-modules are referenced by prepending a dot-separated "path" of module instance names. For instance, suppose there are two instances of a module named "foo" in the root module with instance names "g1" and "g2". Now suppose the "foo" module contains a wire named "w1". These wire names are referenced by the simulator as "g1.w1" and "g2.w1" to distinguish the two instances.

TkGate is an event-driven simulator. Time is measured in discrete units called "epochs". Each gate has a delay of a certain number of epochs. Some complex gates have multiple delay constants. In addition, some gates such as registers and memories have additional delay parameters which affect internal state changes.

The basic simulator commands are:

Function Button Description
Run Enters continuous simulation mode. The simulation will continue as long as there are events in the event queue. If there are any clock gates in your circuit, this will mean the simulation will continue indefinately. If the circuit is combinational, the simulation will continue until the circuit reaches quiescence.
Pause Causes a continuously running simulation to stop.
Step Epoch Causes the simulation to advance a fixed number of epochs. The number of epochs to advance can be set on the simulation options menu. You can also invoke this command with the spacebar.
Step Cycle Causes the simulation to advance to the rising edge of a clock. You can set the number of clock cycles to simulate and the number of epochs past the designated cycle to step (to allow time for registers to change value). The default is to trigger on any clock, but you can designate a specific clock in the simulator options menu. You can also invoke this command with the tab key.
End Simulation Causes the simulation to be terminated and all probes to be deleted.

Other simulator commands will be discussed in the following sections.

3.2 Simulator Options

Several simulation options can be set through the options dialog box. To edit the simulator options, select "Options..." from the "File" menu. The simulator options are in the lower right corner of the dialog box.

The simulator options are:


3.3 Observing the Output

Except when otherwise noted, verilog syntax is used to specify and display values. A Verilog syntax number contains a prefix to specify the bit width, a quote character, a radix character and the digits of the number. The radix characters using in tkgate are "b" for binary, and "h" for hexidecimal. For example "8'h3e" is the 8-bit hexidecimal number "3e". The simulator supports the following logic values:

Symbol Scope Description
0 Logic 0
1 Logic 1
x Unknown
z Floating
L Low (the signal is either floating or zero)
H High (the signal is either floating or one)

To display the value of a signal in a circuit, click and hold the mouse button on a wire. This will display the current value driven on the wire in verilog syntax. The value will disappear when you release the mouse button. This feature can be used both when the simulator is paused and when it is in continuous simulation mode. When the simulator is in continuous simulation mode, the value displayed will be the value at the time the mouse button was first pressed.

To set a permanent probe on a signal, double click on a wire. This will add or remove a probe. When a probe is set on a wire, its value will be continuously displayed in the scope window. The values of multi-bit signals will be displayed as hex numbers. You can use the scroll bars to set move the scope to display early times or you can use the '>' and '<' keyboard commands to expand or compress the time scale.

To print a scope trace, choose the "Print..." option from the "File" menu on the scope window, or use the keyboard shortcut "Ctl-s p". The dialog box shown here will be displayed. The left half of the dialog box is the same as the left half of the dialog box used to print circuits. The right half includes options for selecting the time range to print and the scale factor to use. Beware that simulation traces can grow very large, very quickly, especially when you use the continuous simulation mode. An estimate of the number of pages needed for each trace you have set is displayed to help you set parameters.

3.4 Controlling the Input

There are three types of circuit elements which can be used to control your circuit: the single-bit switch, the multi-bit dip switch and the tty.

3.4.1 Switches and Dip Switches

Switches can be manipulated by simply clicking on them to toggle their values. To change a dip switch value, click on the dip switch to open a dialog box for setting that dip switch. Enter a value in the entry area, and press the apply button to set the switch. The dialog box will remain until you hit close.

3.4.2 Ttys

The third type of input element is the tty. The tty is actually both an input and an output device modeling an interactive terminal. When you start the simulator, one tty window will appear for each instance of a tty gate in your circuit. Your circuit can send characters to and receive characters from the tty gate.

To send a character to a tty element, drive the RD input with the ascii code of the character to transmit and wait for the DTR output to go high. Next assert the DSR signal (positive high). The character will be transmitted on the positive edge of the DSR signal. You must then unassert the DSR signal so that the next character can be sent.

To receive a character, first unassert the CTS signal and wait for the RTS signal to go high. You can then read the value on the TD ouput of the tty. Once you have read the value, assert the CTS signal to indicate that you have received the character.

3.5 Setting Breakpoints

Button
Breakpoints can be used to set conditions which will cause a continuously running simulation to pause. To display the breakpoint dialog box, choose the "Breakpoint..." option from the "Simulate" menu. This will cause the breakpoint editor such as then one shown to the right to be displayed. You can use the button to add, edit or delete breakpoints.

When you add or edit a breakpoint, a breakpint editing dialog box such as the one shown here will be displayed. Enter or edit the breakpoint condition and hit OK. Currently, only a limited number of breakpoint types can be used. Only a single signal can be compared with a constant using a single relational operator. The relational operators are the standard relational operators used in C. The value must be a verilog syntax constant. Alternitively, you can simply type a signal name to break when the signal becomes non-zero, or a sginal name prepended with the '!' operator to break when the signal becomes zero.


3.6 Initializing Memories

A circuit can contain one or more memories (ROM and RAM gates). You can initialize memories from a file, or dump the contents of a memory to a file. Use the options in the table below to load or dump memories.

Function Button Description
Load Memory... Load memories from the selected file. If a memory gate is selected, that memory will be the default memory to load. If the memory file contains one or more "memory" keywords, the specified memory(ies) will be loaded with the contents of the file. When loading a file, the current directory, the directory of the current circuit file, and the user's home directory will be searched.
Dump Memory... Dumps the contents of the selected memory to a file.

Memory files have the extension ".mem" be default. A memory file is composed of a number of lines. Blank lines and lines begining with '#' are ignored. Other lines must be a "memory" declaration or an address in hexidecimal followed by a slash, and a list of memory values in hexadecimal. An example memory file might look like:
100/ e1 f0 0 0 e1 e0 0 0
108/ 81 0 0 0 12 1 bd 0
110/ e 1 e1 d0 dc 7 85 0
118/ 6f 6 81 0 0 0 4e 4
120/ 69 f0 2 0 85 0 64 0
128/ 81 0 0 0 26 4 69 f0
130/ 2 0 ed 0 60 6 62 6
138/ ed 0 5e 6 1 0 85 0
The address at the beginning of the line specifies the address at which to begin storing values. Values are stored sequentially from the specified address one word at a time for the rest of the line.

If there is no "memory" keyword in the memory file, the selected memory gate will be loaded. The memory keyword requires a single argument specifing the name of a memory. For example:

memory memory.m1
100/ e1 f0 0 0 e1 e0 0 0
108/ 81 0 0 0 12 1 bd 0
will load the memory "m1" in the instance named "memory" which is a submodule of the root module. In order to assist in creating memory files, you can use gmac to compile microcode and macrocode descriptions into TkGate-compatable memory files.

For RAM memories, the contents of the loaded memory are frozen until first time the write line transitions to a stable value (logic 0 or 1). This prevents the data loaded from being destroyed due to unknown values on the write and address lines until the circuit has time to intitilize these signals.

3.7 Simulation Scripts

Button
Simulation scripts can be used to perform most of the operations you can do manually. You can set and remove probes, change switch values, load memories, set breakpoints, and step and start/stop the simulator. Simulation script are useful for setting up a simulation before starting, or for running a simulation in batch mode. You can load a simulation script using the button on the button bar or by selecting "Exec. Script..." from the "Simulate" menu. The default extension for simulation scriptes is ".gss". When loading a file, the current directory, the directory of the current circuit file, and the user's home directory will be searched.

You can also arrange for simulation scripts to be automatically executed when you start the simulator either by specifying a simulation script in the simulation options dialog box, or by adding simulation scripts as circuit options. The following simulation script commands are recognized. Arguments specified between "?" characters denote optional arguments.


Command Description
include "file" Includes the specified file as if its contents appear here in the simulation script.
step n Steps the specified number of epochs.
clock(+/-) ?[name]? n ?+m? Step n clock steps. If the character after "clock" is a "+" stepping will be on positive clock edges. If the character is a "-" the stepping will be on negative clock edges. If name is specified, only edges on that clock will be used. If m is specified, then the simulator will step that number of epochs after the final clock edge.
run Put the simulator into continuous simulation mode. This command will block until a breakpoint is hit, or until you press the pause button.
break ?[name]? cond Sets the breakpoint cond which must have the syntax described in the section on breakpoints. If a name is specifed in square brackets. This breakpoint will be assigned a symbolic name which can be referenced to deleted the breakpoint later. If no name is specified, then it will not be possible to remove the breakpoint from a simulation script.
delete [name] Deletes the specified breakpoint. Only breakpoints set through a simulation script and assigned a symbolic name can be deleted.
set name value Sets the value of a switch or dip switch. Name should specify the full path of a switch or dip switch, and value should be a verilog syntax constant.
probe name Sets a probe on signal name. The name should be specified as a full path.
unprobe name Removes the probe on signal name. The name should be specified as a full path.
load ?name? "file" Load memories from a file. If you specify a memory name, that memory will be the default memory.
dump name "file" Dumps the contents of the specified memory to a file.

3.8 Using the Error Reporter

If there are any errors in the circuit when you start the simulator. An error list box will appear with the list of errors and the modules in which these errors occured. You can scan through the list of errors using the "Ctl-n" and "Ctl-p" keyboard commands. TkGate will go to the module in which the current error occured and highlight the position of the error with an "X" symbol.

3.8 Gate Delay Specification File

Custom gate delays can be specified through the TkGate options box. The specified file should contain a list of "delay" commands indicating the delays for each of the gate types. A delay command consists of the "delay" keyword, the name of the gate type, the delay parameter enclosed in angle brackets, the '=' symbol and an integer delay value. For example, delay times for a multiplexor can be set with the delay times.
delay mux<S-Z> = 20
delay mux<I-Z> = 10
The first command sets the delay from the S input to the output to 20, and the second command sets the delay from any of I inputs to the output to 10. You can also specify '*' for the delay parameter to set all delays for a gate type to the same value. Comments in a delay file are indicated by lines starting with '#'.

A current limitation of TkGate delays is that it is not possible to specify delay as a function of the number of inputs, or of port bit widths. For example, a 4-bit adder will have the same delay as a 32-bit adder. Also, inverting input and output are not considered in calculating delay.

Gate TypeParameterDefaultDescription
and I-Z 5Delay from input to output.
or I-Z 5Delay from input to output.
xor I-Z 5Delay from input to output.
buf I-Z 3Delay from input to output.
bufif1 E-Z 3Delay from enable to output.
I-Z 5Delay from data input to output.
nmos I-Z 3Delay from data input to output.
G-Z 2Delay from gate to output.
pmos I-Z 3Delay from data input to output.
G-Z 2Delay from gate to output.
add A/B-S 30Delay from operand input to sum.
A/B-CO 35Delay from operand input to carry out.
CI-S 35Delay from carry in to sum.
CI-CO 40Delay from carry in to carry out.
register setup 10Time before clock edge data-in must be stable.
hold 10Time after clock edge data-in must remain stable.
CK-Q 20Time from clock edge until output changes.
mux S-Z 20Delay from select line to output.
I-Z 10Delay from data input to output.
demux E-Z 10Delay from enable line to output.
I-Z 25Delay from data input to output.
mult A/B-Z 60Delay from operand input to output.
div A/B-Q 80Delay from operand input to quotient.
A/B-R 80Delay from operand input to remainder.
ram OE-D 10Delay from output enable to data-out.
CS-D 10Delay from chip select to data out.
A-D 70Delay from the address line to the data out.
addr_setup 10Time before write is asserted that address must be stable.
data_setup 10Time before write is asserted that data-in must be stable.
addr_hold 10Time after write is unasserted that address must remain stable.
data_hold 10Time after write is unasserted that data-in must remain stable.
rom OE-D 10Delay from output enable to data-out.
A-D 50Delay from address to data-out.
tty TR 150Time to transmit a character.
RTS_UP 2Time after transmition is complete before RTS line is raised.
RTS_DN 8Time after DSR is asserted that RTS will fall.
RD 150Time to read a character.
DTR_UP 2Time after character is received that DTR will be raised.
DTR_DN 2Time after CTS is asserted that DTR will fall.
lshift S-Z 10Delay from shift select to output.
I-Z 12Delay from data-in to output.
rshift S-Z 10Delay from shift select to output.
I-Z 12Delay from data-in to output.
arshift S-Z 10Delay from shift select to output.
I-Z 12Delay from data-in to output.
roll S-Z 10Delay from shift select to output.
I-Z 12Delay from data-in to output.